Multi-core processors, when used for certain applications, may consume a large amount of power. This is especially true with the increasing number of cores in multi-core processors. To enhance power efficiency in the face of ever-increasing number of cores, multi-core processors may run at lower voltages. While running at lower voltages may reduce the power consumption of multi-core processors, running the processors at lower voltage may decrease the number of usable cache lines, and therefore increase the probability of cache misses, namely, read and/or write errors of the cache.
FIG. 1 illustrates a multi-core processor 10 that include three levels of caches. The multi-core processor 10 may include a number of cores 12.112.4 that may each include a processing engine (not shown). The processor 10 may also include three levels (L1, L2, L3) of cache memories 14.1-14.4, 16, 18 for locally storing instructions and data. Instructions and data may be pre-fetched from the main memory 22 and stored locally in these three levels of caches so that the instructions and data may be accessed by processing engines locally from these caches rather than remotely from the main memory through the slow data bus 24.
Caches in the multi-core processor 10 may be organized according to hierarchical levels. Referring to FIG. 1, at the highest level, Level-3 (L3) cache 18 may be the main cache storage that may be shared by all cores 12.1-12.4 that may access cache 18 via an interconnect fabric 20. Although access to the L3 cache 18 via the interconnect fabric 20 is faster than access to the main memory 22 via bus 24, the access to the L3 caches 18 may still not fast enough for those frequently-accessed instructions and data. To this end, processor 10 may include, at the lowest level, Level-1 (L1) caches 14.1-14.4, each of which is within a respective core 12.1-12.4 so that the processing engine of the respective core may access instructions and data stored in the L1 caches 14.1-14.4 locally within each core and thus faster. The intermediate Level-2 (L2) cache 16 may be local to some cores (e.g., 12.1, 12.2), but not to all of the cores. In practice, L3 cache 18 usually have larger size, while Level-1 cache 14.1-14.2 are usually much smaller.
Each core 12.1-12.4 may run at a specific voltage (Vmin) and frequency (Fmax), which may be adjusted to allow the multi-core processor 10 working at different states. As discussed above, to reduce the power consumption for the multi-core processor 10, at least some of the cores 12.1-12.4 may run at a lower Vmin. For example, the cores may run at a near threshold voltage (NTV) of a core at approximate 590 mv rather than at around 700 mv for the normal operation.
Although running at lower voltage may save power, the lower voltage also increases the probability of cache failures or errors in caches read and/or write operations. Processors of current art may use a variety of error detection and correction mechanisms to counter cache misses and to ensure the integrity of instructions and data stored in the caches. Error-correction codes (ECC) are often used for L3 and L2 caches to ensure the correctness of the instructions and data stored therein. However, the smaller L1 caches are typically only protected with parity check which allows for only error detection but no correction. ECC is not used for L1 caches for two reasons. First, L1 caches support fast byte read and write to which ECC may require a large area overhead (e.g., up to 50% for correcting even a single error). Second, the latency overhead for applying ECC to L1 caches may also become significant and thus impractical.
In addition to the power consumption consideration, a multi-core processor may also age over the life cycle, which may also cause Vmin to become higher than the optimal operating voltage and thus cause cache errors. These cache errors are an especially prominent problem for L1 caches since L1 caches do not usually have error correction.